32位单精度浮点乘法器的FPGA实现

Implementation of 32-bit Single Precision Floating Point Multiplier Based on FPGA

采用V erilog HDL语言,在FPGA上实现了32位单精度浮点乘法器的设计,通过采用改进型Booth算法和W a llace树结构,提高了乘法器的速度。本文使用A ltera Q uartus II 4.1仿真软件,采用的器件是EPF 10K 100EQ 240 1,对乘法器进行了波形仿真,并采用0.5 CM O S工艺进行逻辑综合。

Using Verilog HDL,a design of 32 b single precision floating point multiplier based on FPGA is presented. By using a structure of Wallace trees and Booth algorithm,the speed of multiplier has been improved. The software of Altera Quartus Ⅱ 4.1 is used for performing the wave simulation of the multiplier with EPF10K100EQ240 - 1 device. The multiplier is synthesized with 0. 5 CMOS technology.