基于FPGA的数据采集系统设计

Design of Data Acquisition System Based on FPGA

设计了以FPGA为核心逻辑控制模块的高速数据采集系统。设计中采用了自顶向下的方法,将FPGA依据功能划分为几个模块,详细论述了各模块的设计方法和控制流程。FPGA模块设计使用VHDL语言,在M ax+P lusⅡ中实现软件设计和完成仿真。本文给出了一些模块的仿真图形。整个采集系统可实现24路最大工作频率为100 kH z的现场模拟信号采集和4路频率信号采集,且该系统也采集8路系统内部通道信号以达到自校验功能。

The high speed data acquisition system based on FPGA, which is the core logic control module of the system is designed. According the method of top -down,FPGA is divided into some functional modules. The desi＇gning method and controlling flow of each module are discussed in detail. The VHDL language is adopted in the FPGA module. Software design and system simulation are completed in the integration circumstance of Max＋Plus Ⅱ . The paper provides the simulation figures of some FPGA modules. The system not only can acquire 24-route field analog signals with 100 kHz of maximal frequency and 4-route frequency signals,but also has the ability of self-check by acquiring 8-route inner channel signals.