一种分像素运动补偿插值滤波方法及高效VLSI实现

A Sub-Pixel Motion Compensation Interpolation Method and Its High Performance VLSI Design

现代视频编码标准普遍采用变换与运动补偿预测混合型编码架构,该架构对运动补偿预测后的残差图像和运动矢量等信息进行变换编码,运动补偿预测的准确度对编码性能有显著影响.由于实际对象的运动精度是任意小的,允许运动矢量具有“分像素”精度,可以有效地提高运动补偿预测准确度,为了得到“分像素”位置的像素值,需要参考其周围相邻的像素值进行插值滤波.文中提出了一种低空间复杂度1/4像素插值方法两步四抽头插值法(Two Steps Four Taps Interpolation,TSFT),该方法与目前国际上最先进的视频编码标准H.264/AVC相比,可以降低11%的空间复杂度,计算复杂度和编码效率相当,已经被国内制定的编码标准AVS1.0采纳.另外,分像素插值是解码端主要的访存和计算瓶颈,文中给出了一个基于多级流水线结构的VLSI实现结构,可以降低访存带宽,同时提高插值器的运算速度,满足高清视频实时解码的需要.

Transform and motion compensation hybrid coding structure is commonly adopted in modern video coding standards, which transforms the residues and codes motion vectors. The accuracy of motion compensation is the key technique in this coding scheme. As real motion has arbitrary precision, allowing motion vectors to have ＂sub-pixel＂ resolution can greatly improve the prediction accuracy. In order to estimate and compensate sub-pixel displacements, the image signal on sub-pixel position has to be generated by interpolation. This paper proposes a quarter-pixel interpolation method named as Two Steps Four Taps interpolation（TSFT）, compared with interpolation method in H. 264, 11% spatial complexity is reduced, computation complexity and average SNR is about the same. It has been adopted by the coding standard AVS1.0. In addition, sub-pixel interpolation is the computing and memory access bottleneck of video decoder. This paper proposes a VLSI architecture based on multiple stages pipeline, which reduces the bandwidth while accelerates interpolation operation and satisfies real-time decoding of HDTV sequences.