基于复杂可编程逻辑器件的数字频率计的设计与实现(英文)

Design and Implementation of Digital Cymometer Based on CPLD

采用自上向下的设计方法,设计了基于复杂可编程逻辑器件的数字频率计.以AT89C51单片机作为系统的主控部件,完成电路的测试信号控制、数据运算处理、键盘扫描和控制数码管显示.用VHDL语言编程,由CPLD(Complex Programmable Logic Device)EPM 7128SLC 84-15完成各种时序控制及计数功能.该系统具有结构紧凑、可靠性高、测频范围宽和精度高等特点.

With the adoption of the top-down design method and AT89C51 SCMC （Single Chip Mico Computer） as the master control component of the system,the circuit test signalcontrolling,data operation processing,keyboard scanning, and nixie tube display as well were completed by the digital cymometer. A CPLD, EPM7128SLC8415,programmed by VHDL,realized various sequence control and count functions. The system is characterized by impact structure, high reliability, high precision, and wide frequency-test-range.