一种用于FPGA流水线设计的时钟技术

A Clocking Technique Used in FPGA Pipelined Designs

介绍了一种时钟流水线技术———单脉冲流水线(PP-流水线),它可用于在FPGA中实现异步流水线操作。加入数据完成电路,利用可变的数据处理时间,这种技术亦可用于同步流水线设计。PP-流水线还可以降低流水线电路的时钟树功耗。这些应用可通过FPGA电路的综合后模拟得到验证。

This paper presents a clocking pipeline technique referred to as a single- pulse pipeline （PP- Pipdine）. It can be applied to the operation of asynchronous micropipdine in FPGA devices. The technique can be extended to include data - completion circuity to take advantage of variable data- completion processing time in synchronous pipelined designs. It is also shown that the PP- pipeline reduces the clock tree power consumption of pipelined circuits. These potential applications are demonstrated by post - synthesis sirnulation of FPGA circuits.