一种基于SoC的MPEG-4视频解码加速器

A MPEG-4 Accelerated Video Decoder Based on SoC

实现了一种应用于系统芯片(SoC)的M PEG-4视频解码加速器。该解码器可完成M PEG-4解码中计算量最大的离散余弦变换(IDCT)、反量化(inverse quan tization)和运动补偿叠加(reconstruction)。本文通过算法、总线接口、存储器结构以及硬件开销方面的优化,使得在满足M PEG-4实时解码的基础上,加速器占用SoC系统芯片的总线带宽和硬件面积尽量的小,并有利于存储器的复用。经实验验证,本设计可以对M PEG-4简单层(sim p le profile)实时解码。

A design of MPEG-4 accelerated video decoder based on SoC is presented. The IDCT which has the most calculation in MPEG-4 decoding, inverse quantization and reconstruction, is implemented. In this design, algorithm, bus interface, memory architecture and chip area are optimized. So on the basis of meeting the requirement of real time decoding, low SoC bus bandwidth occupation and high level memory reuse have been achieved.