期刊文献+

低功耗0.35μm CMOS 2.5Gb/s 16∶1复接器设计 被引量:2

Design of Low Power 2.5Gb/s 16∶1 MUX with 0.35μm CMOS
下载PDF
导出
摘要 采用0.35μm CM O S工艺设计了用于光纤传输系统的低功耗16∶1复接器,实现了将16路155.52M b/s数据复接成一路2.5G b/s的数据输出的功能。该复接器以混合结构形式实现:低速部分采用串行结构,高速部分采用树型结构。具体电路由锁存器、选择器及分频器组成,以CM O S逻辑和源极耦合逻辑(SCL)实现。用Sm art SP ICE软件进行仿真的结果显示:在3.3V供电时,整体电路的复接输出最高工作速度可达3.5G b/s,功耗小于300mW。 A low power 16 : 1 MUX (multiplexer) for optical-fiber-transmission system designed with 0.35vm CMOS technology is presented in this paper, it can realize the function of 16 data inputs of 155.52Mb/s to 1 data output of 2.5Gb/s. The MUX is constructed in the combined style of serial-type architecture in low speed part and tree-type in high speed part. The concrete circuits are composed of latches, selectors and frequency dividers. They are implemented with CMOS logic and source coupled logic (SCL). The simulation of the MUX in Smart SPICE shows that the highest speed of the output can reach 3.5Gb/s and its power dissipation is less than 300mW under 3.3V power supply.
作者 凌云 冯军
出处 《电气电子教学学报》 2005年第6期50-53,72,共5页 Journal of Electrical and Electronic Education
关键词 CMOS 源极耦合逻辑 复接器 低功耗 光纤传输 CMOS source coupled logic MUX (multiplexer) low power dissipation, optical-fiber-transmission system
  • 相关文献

参考文献4

  • 1Lu Jianhua,Tian Lei,et al Design Techniques of CMOS SCL circuits for Gb/s Applications[C].ASIC 2001 Proceedings,4th International Conference on 23-25 Oct.2001.
  • 2JanM Rabaey.数字集成电路设计透视(影印版)[M].北京:清华大学出版社,1998..
  • 3BehzadRazavi 陈贵灿 译.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2002..
  • 4ZhangCheng-an SongQi-feng.2.5Gb/s 16:1 MUX IC Design with CMOS.Semiconductor Photonics and Technology(半导体光子学与技术:英文版),4.

共引文献1

同被引文献12

引证文献2

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部