一种高速低功耗内容寻址存储器的设计

Design of A High-speed Low-power CAM

提出了一种适用于TLB的低功耗内容寻址存储器电路,该电路用两级比较的方法实现TLB的查找功能.由功耗模型的分析得到低功耗CAM的最优设计参数,通过减小电压摆幅的办法进一步降低功耗.电路在0.18μm 1P6M标准CMOS工艺上实现,仿真结果表明64路TLB的最大比较延迟为0.983 ns,功耗为4.59μW/bit.

A low power content addressable memory （CAM） is presented. Two-stage comparison results in good performance in TLB and the optimum design parameters of low power CAM are determined by the power model analysis. Lower voltage swing is also used to further reduce the power dissipation. The circuit is implemented in 0.18 μm 1P6M CMOS process. Simulation results show that the circuit consumers 4.59μw/bit while the maximum delay is 0. 983 ns in 64 entry TLB.