一种新结构的判决反馈时序估计电路

A New Architecture of Decision Feedback Sequence Estimator

千兆以太网的四维8状态网格编码提供了无干扰无噪声情况下的6 dB信噪比增益,判决反馈时序估计电路被用于消除后馈干扰、抑制噪声及译码.从信噪比与误码率、关键路径与速度及硬件复杂度等方面模拟比较了该电路的几种实现形式,提出了一种预均衡器与流水线并行判决反馈译码器的混合式结构,它能获取5.3 dB的信噪比增益从而降低误码率,并以合适的硬件代价达到协议规定的125 MHz速度要求,同时确定了利用这种混合结构实现判决反馈时序估计电路的主要设计参数.

4D 8-state trellis encoding of 1000 Base-T provides 6 dB coding gain in an inter-symbol interfere（ISI） and noise free channel. Decision feedback sequence estimator（DFSE） is used for post-eursor ISI compensation, noise erasion and decoding. Different architectures of DFSE have been simulated and compared according to signal noise ratio（SNR） and bit error ratio（BER）, critical path and speed, and hardware cost as well. An hybrid architecture consisting of preequalizer and pipelined paralleled decision feedback decoder is proposed for the implementation of DFSE, which yields about 5.3 dB coding gain and consequently low BER, and meets 125 MHz timing budget at reasonable hardware cost. In addition, the main parameters of the hybrid architecture are also determined.