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高速浮点乘法器设计 被引量：7

Design of high speed floating-multiplier
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摘要 设计了一种符合IEEE-754标准的32bits高速CMOS浮点乘法器。该乘法器采用MBA算法和基于4:2compressor的树型结构完成CarrySave形式的部分积压缩,再由高速CarrySelect加法器求得乘积。电路设计采用了新型的高速加法运算单元。乘法器采用0.35μm制程,内含19,197个晶体管。3.3V工作电压下(室温),乘法器延迟时间为3.807ns,功耗为107mW@100MHz。 A high-performance lEEE-compliant 32-bits floating-point multiplier design has been presented in this paper. Modified booth＇s algorithm and the 4：2 tree reduce the carry save partial products to sum and carry vectors, then a fast final carry select adder convert the sum and carry vectors to conventional format. We also present a novel adder cell which offers faster operation. This multiplier was simulated by 0.35μm CMOS technology. The number of transistors is 19,197. The operating cycle time is 3.807ns at the supply voltage of 3.3V and room temperature. Only 107mW power dissipation needed at the operating frequency of 100MHz.
作者 吴金 应征
机构地区 东南大学无锡分校 东南大学微电中心
出处 《电路与系统学报》 CSCD 北大核心 2005年第6期6-11,共6页 Journal of Circuits and Systems
关键词 乘法器 Modified BOOTH algorithm 4:2 COMPRESSOR ROUND full ADDER multiplier modified booth algorithm 4：2 compressor round full adder
分类号 TN47 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献16

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二级参考文献6

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同被引文献30

  • 1李小进,初建朋,赖宗声,徐晨,景为平.定点符号高速乘法器的设计与FPGA实现[J].微电子学与计算机,2005,22(4):119-121. 被引量：3
  • 2赵倩,汤乃云,韩桂泽.基于流水线重构技术的16x16位乘加器的设计[J].微计算机信息,2006,22(12Z):302-304. 被引量：3
  • 3李磊,赵建明.高速可重组16×16乘法器的设计[J].微电子学与计算机,2007,24(6):120-122. 被引量：5
  • 4ANSI/IEEE Std.754-1985,IEEE Standard for binary Floating-Point Arithmetic [S].IEEE, Inc, New York, 1985.
  • 5Kiseon Cho, Jongon Park, Jinseek Horg. 54 × 54 - bit radix-4 multiplier based on modified booth algorithm[J]. IEEE Solid-State Circuits, 2003,25(3) : 233-236.
  • 6Dozza D, Gaddoni M, Baeearani G. A 3.5ns, 64 bit carry - lookahead adder [ C ]//Proceedings of IEEE International Symposi- um on Circuit and Systems. 1996:297 -300.
  • 7Matthew S, Krishnamurthy R, Anders M, et al. Sub -500ps 64 - b ALUs in 0.18 mm SOI/Bulk CMOS: design and scaling trends [ J]. IEEE Journal of Solid - State Circuits, 2001, 36 ( 11 ) : 1 636 - 1 646.
  • 8Mathew S, Anders M, Krishnamurthy R, etal. A 4GHz 130 nm address generation unit with 32b sparse - tree adder core [J]. IEEE Journal of Solid - State Circuits, 2003, 38 (5) : 689 - 695.
  • 9Mathew S K, Anders M A, Bloechel B, etal. A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm C MOS [ J ]. IEEE Journal of Solid - State Circuits, 2005, 40 ( 1 ) : 162 - 163.
  • 10Jin Zhan - peng, Shen Xu - bang, Bai Yong - qiang. A 64 - bit fast adder with 0.18 μm CMOS technology [ C]//Proceedings of IEEE International Symposium on Communications and Information Technologies. Beijing: [ s. n. ], 2005:1 167 -1 171.

引证文献7

二级引证文献10

电路与系统学报
2005年 第6期

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