基于Verilog-A行为描述模型的VCO设计

Design of VCO based behavioral model using Verilog-A

分析了模拟硬件描述语言Verilog-A的特点,介绍了基于Verilog-A语言的行为级模拟电路设计过程。以锁相环(PLL)的子模块压控振荡器(VCO)的设计为例,建立了基于Verilog-A的行为模型进行系统设计的新方法。根据VCO的数学模型,建立了中心频率为120MHz的VCO行为模型,并利用CadenceSpectre仿真器对该模型进行了验证及PLL系统仿真。

The characteristics of Verilog-A HDL are introduced and the flow of system level simulation using Verilog-A behavioral model is analyzed. Based the mathematical analysis, some parameters are confirmed and the behavioral model of VCO with 120MHz center frequency is implemented by this method. The behavioral model are verified and used in PLL system simulation by the tool of Cadence Spectre.