嵌入式处理器中的Sector Cache:性能与面积的折衷

Sector Cache for Embedded Processor: a Tradeoff Between Performance and Area

SectorCache曾经被用于一些最早使用Cache技术的计算机系统中.虽然SectorCache的性能略差于普通Cache,但同样Cache容量下Sector结构所需的标记位明显少于普通结构.由于嵌入式处理器对芯片面积的要求非常严格,SectorCache的优点在嵌入式处理器中就更为明显.本文用基于仿真的方法详细分析了Sector结构的Cache在嵌入式应用环境下的性能.仿真结果表明,合理使用Sector结构可以以较小的性能代价有效地减少标记位数量.因此,采用SectorCache就可以在满足性能要求的前提下尽可能减小Cache控制器的面积.本文认为SectorCache是嵌入式处理器设计者进行性能/面积折衷有效手段.

Sector cache was adopted by some early computer systems. Although the now popular set-associative structure has better performance than sector structure, sector structure have the advantage that large number of bytes can be controlled using relative small number of tag bits while keeping the block size small. Since embedded processors have strict limit to its chip area, sector cache＇s feature is very useful for embedded processor. Using a simulation based method, this paper analysis the performance of sector cache in embedded applications. The result shows that using sector cache properly can largely reduce tag bits at little performance cost. Using sector cache, we can reduce the area of cache controller while meet the performance request. In conclusion, we find that sector cache is a good method for design tradeoff between performance and area for embedded processors.