中间表示设计中基于链表的多寄存器操作数处理

Multi-registers Operands Handle Based on Chain for Intermediate Representation Design

以简单但具有代表性的配对寄存器为例,分析了编译器中间表示设计中使用配对信息所需包含的要点。结合编译器中数据流分析,指令调度和寄存器分配的需求,进一步提出了一种基于链表结构的中间表示及构造算法。所提出的表示方法同时考虑到编译器的可移植性,以便于在不同编译器中实现。

This paper focuses on the design of intermediate representation and puts forward an intermediate representation for pair register based on chain. First, it analyzes the points that 1R design should handle when adapts to pair registers. Then, it puts forward a chain-based 1R when considering the demand of data flow analysis, instruction scheduling and register allocation. At last, an algorithm is given. Retarget is another important phase and the paper tries to figure out a common 1R for the chips with multi-register operands.