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高性能LS-DSP的逻辑设计与低功耗设计 被引量:2

The Design of Logic and Low Power for LS-DSP
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摘要 LS-DSP是面向数据密集型和控制密集型处理应用的需要,而开发的高性能数字信号处理器。本文主要介绍LS-DSP内有特点的逻辑设计技和低功耗设计技术。LS-DSP采用0.18ΜMCMOS工艺制造,集成度为1000万器件,芯片面积5×5MM2,主频为120MHZ,典型应用的平均动态功耗为325.084MW。 LS-DSP is designed for data and control denseness process application. This paper describes the design technology of logic and low power in LS-DSP. It is fabricated in a 0.18urn COMS process, it has 10 million device ,the area is 5×5mm^2, and the operation frequency can reach 120MHz, the average dynamic power dissipation of typical application is 325.084mw.
出处 《微电子学与计算机》 CSCD 北大核心 2006年第1期15-20,24,共7页 Microelectronics & Computer
关键词 数据路径 ALU 乘法器 地址产生器 总线低功耗 海明距离 Data path, ALU, MultipUer, Address generator, Bus low power, Hamming distance
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