Si-SiO_2界面陷阱引起的双极晶体管h_(FE)漂移的模型与模拟

Modeling and Simulating for Drift of h_FE of the Bipolar Transistors Induced by the Si-SiO_2 Interface Trap

本文表明,Si-SiO_2界面过渡层中的载流子陷阱对硅体内电子存在慢俘获作用,这将导致npn型双极晶体管电流放大系数h_(FE)随时间的正向漂移。从这种物理机制出发,建立了相应的数学模型。经计算机模拟分析,求得了h_(FE)随时间的漂移曲线以及温度、发射结偏压、基区表面势对这种漂移的影响。结果表明,基区表面势对漂移量的大小有重要影响,高温老化是漂移失效筛选的有效手段。

It is presented in this paper that dc current gain hFE of npn bipolar transistors drifts with time due to the slow trapping effect in the Si-SiO2 interface transition layer on the electron in the Si-substrate. The drift model for the mechanism is developed. As a result of the computer simulation, the drift curve of hFE with time and the effects of temperature, emitter bias voltage, and base surface potential on the curve are given. It is shown that the effect of base surface potential is most evident, and high temperature agiag is an effective method of the drift failure screening.