一种适于VLSI实现的并行乘法器结构

A Parallel Multiplier Configuration Suitable for VLSI Realization

本文首先讨论了数据格式与改进Booth算法的关系。用简化部分积的扩展符号位所在全加器的连接的方法提出了一种适于VLSI实现的并行乘法器结构。该结构已用于16×16和12×12高速乘法累加器的全定制设计中。

The relationship between data format and the modified Booth's algorithm is discussed. A parallel multiplier configuration especially suitable for VLSI realization is presented. The configuration has been employed in the design of the 16×16 and 12 × 12 fully custom multiplier-accumulators.