单片BiCMOS超高频接收机中锁相环的设计(英文)

BiCMOS PLL Frequency Synthesizer for UHF Receiver

集成电荷泵锁相环的接收芯片工作在ISM频段:290～470MHz,采用AMS 0.8μm BiCMOS工艺,npn管的特征频率为12 GHz,横向pnp的特征频率为650 MHz.锁相环中鉴频鉴相器和电荷泵的设计方案基本消除了死区.压控振荡器采用LC负阻结构,中心振荡频率为433 MHz,调谐范围为290～520MHz,频偏为100 kHz时的相位噪声约为-98 dBC/Hz.分频器采用堆叠式结构以降低功耗,PLL在5 V的工作电压下功耗仅为1.4 mA.

This paper describes the design of a low power charge pump phase-locked loop （CPPLL） frequency synthesizer circuits which provide local oscillator for mixer in receiver. The receiver working at ISM band from 290 MHz to 470 MHz is implemented in the AMS 0. 8 tzm BiCMOS process with 12 GHz npn transistor and 650 MHz lateral pnp transistor. The CPPLL circuit uses a digital phase-frequency detector （PFD） which provides a wide frequency acquisition capability. An on-chip charge pump is designed for no dead zone. The LC-tuned negative-resistance voltage controlled oscillator （VCO） has a measured center frequency of 433 MHz and a tuning range 290-520 MHz. A stack mode divider is designed for low power. The total power consumption of CPPLL is 1.4mA with 5V supply voltage.