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差分LC VCO的设计方法 被引量：5

Design Method in Optimization Differential LC VCO
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摘要 通过分析振荡器的两种典型相位噪声模型,给出了振荡器相位噪声与电路参数的关系。在此基础上,提出了优化VCO相位噪声的设计方法:设计高Q值电感;调整尾电流的大小;调整nMOS管和pMOS管的尺寸。文章最后给出了一个24GHz全集成VCO的设计,仿真结果表明在2.4GHz时VCO的相位噪声为-120.4dBc/Hz@600kHz,证明该方法对于VCO的设计具有较好的指导作用。 An analysis of two famous oscillator phase-noise modules derives the relations between phase-noise and circuit parameters. And hence, a design strategy to optimize the phase noise of VCO, such as designing high Q inductor, adjusting tail current and sizing the dimensions of nMOS and pMOS, is presented. At the end of this paper, a 2.4GHz fully integrated VCO design is mentioned. The simulation result describes that the phase noise of the VCO is -120.4dBc/HzG 600 kHz. This result proves that the method is valid.
作者 满家汉 赵坤
机构地区 中国科学院微电子研究所
出处 《电子器件》 EI CAS 2005年第4期809-812,共4页 Chinese Journal of Electron Devices
关键词 集成LC压控振荡器 噪声 相位噪声 锁相环 integrated LC VCO noise phase noise phase-locked loop
分类号 TN75 [电子电信—电路与系统]
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参考文献12

  • 1Craninckx J and Steyaert M.A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors[J].IEEE J Solid-State Circuits,May 1997,32:736-744.
  • 2Niknejad.Analysis,Simulation,and Applications of Passive Devices on Conductive Substractes[D].PhD thesis,University of California at Berkeley,2000.
  • 3Maget J,Tiebout M,Kraus R,MOS Varactors With n-and p-Type Gates and Their Influence on an LC-VCO in Digital CMOS[J].IEEE J Solid-State Circuits,July 2000,38:1139-1147.
  • 4Andreani P,Mattisson S,On the Use of MOS Varactors in RF VCO's[J].IEEE J.Solid-State Circuits,June 2000,35:905-910.
  • 5Hung C and Kenneth K O,A packaged 1.1-GHz CMOS VCO with phase noise of 126 dBc/Hz at a 600-kHz offset[J].IEEE J.Solid-State Circuits,Jan.2000,35:100-103.
  • 6Berny A D,Niknejad A M and Meyer R G,A Wideband Low-Phase-Noise CMOS VCO[C].In:IEEE Custom Integrated Circuits conference,pp.555-558,2003.
  • 7Leeson D B,A simple model of feedback oscillator noises spectrum[J],Proc.IEEE,Feb.1966,54:329-330.
  • 8Razavi B,A study of phase noise in CMOS oscillators[J].IEEE J Solid-State Circuits,Mar.1996,31:331-343.
  • 9Hajimiri A and Lee T H,A general theory of phase noise in electrical oscillators[J].IEEE J.Solid-State Circuits,Feb.1998,33:179-194.
  • 10Dai L,Harjani R,Design of High-performance CMOS Voltage-controlled Oscillators[M].Kluwer Academic Publishers,2003.

同被引文献30

  • 1李仲秋,胡锦,陈迪平.三阶电荷泵锁相环的稳定性分析[J].电子器件,2006,29(2):483-485. 被引量：5
  • 2程梦璋,景为平.锁相环中的充电泵电路的研究[J].电子器件,2007,30(4):1226-1229. 被引量：1
  • 3Randalt W R.Oscillator design and computer simulation[M]. Hardcover, Prentice Hall, 1995.
  • 4Kobayashi K W,Oki A K,Tran L T,et al.A 108 GHz InP- HBT monolithic push-push VCO with low phase noise and wide tuning bandwidth [J].IEEE Journal of Solid-State Circuits, 1999,34(9) : 1225-1232.
  • 5拉扎维.射频微电子[M].北京:清华大学出版社,2003.
  • 6Hajimiri A,Lee T H.A general theory of phase noise in electrical oscillators [J]. IEEE Journal of Solid-State Circuits, 1998,33(2) : 179-194.
  • 7Keliu Shu. A 2.4 GHz monolithic fractional-N frequency synthesizer with pobust phase-switching prescaler and loop capacitance multiplier[J].IEEE Journal of Solid-state Circuits, 2003, 38 (6):866- 874.
  • 8Adrian Maxim. A 2-5 GHz low jitter 0.13p. m CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter[C]. IEEE 2004 Custom Integrated Circuits Conference, 2004: 147- 150.
  • 9Hung Chih-Ming. A fully integrated 1.5 V 5.5 GHz CMOS phase-locked loop[J]. IEEE Journal of Solid- state Circuits, 2002,37(4) : 521-525.
  • 10Shu Keliu. A 2.4 GHz Monolithic Fractional-N Frequency Synthesizerwith Robust Phase-Switching Prescaler and Loop Capacitance Multiplier[ J]. IEEE Journal of Solid-State Circuits,2003,38 ( 6 ) : 866-874.

引证文献5

二级引证文献7

电子器件
2005年 第4期

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