VHDL设计中电路简化问题的探讨

The Inquiry into the Problem of Circuit Simplification in VHDL Design

从描述方法、设计规则、逻辑函数分析了VHDL设计中容易引起电路复杂化的原因,并提出了相应的解决方法.

This article analyze the reason that easily cause circuit complication in VHDL design from description, design roles and logical functon. It also put forward the corresponding solutions.