基于BUFGMUX与DCM的FPGA时钟电路设计

Clock Circuit Design in FPGA Based on BUFGMUX and DCM

与ASIC(专用集成电路)的时钟电路相比,基于FPGA(现场可编程门阵列)的时钟电路有其自身的特点。FPGA一般提供专用时钟资源搭建时钟电路,相应的综合工具也能够自动使用这些资源,但是针对门控时钟和时钟分频电路,如果直接使用综合工具自动处理的结果,会造成较大的时钟偏差。通过合理使用DCM(数字时钟管理单元)和BUFG-MUX(全局时钟选择缓冲器)等FPGA的特殊资源,手动搭建时钟电路,可以尽可能地减少时钟偏差对电路时序的影响。

Clock circuit based on FPGAs has its own features compared with circuit based on ASICs. In general,special timing resources are provided by FPGA devices ;corresponding synthesis tools,meanwhile,it can use such resources automatically. However, the gated clock and clock division circuits that directly come out from automatic synthesis will cause a big clock skew. By reasonably using the special resources in FPGA,such as DCMs （Digital Clock Manager） and BUFGMUXs （global clock MUX buffer） and manually building up a proper clock circuit,the interference to timing caused by clock skew is mostly reduced.