SoC设计中的低功耗逻辑综合策略

A Low Power Consumption Logic Synthesis Strategy for Design of System-on-Chip

介绍了一种SoC(片上系统)电路的高效逻辑综合方法,用工具对功耗关键模块插入时钟门控单元来降低功耗,并用工具提取不带时钟门控模块的约束条件来优化相应带门控的模块,使SoC在最高主频率、面积和功耗等方面达到最优,且时序收敛较快。采用该方法对Unity805plus SoC芯片进行综合,取得比自顶向下、自底向上等传统综合方法更好的效果,在最差情况下最高频率为200 MHz,面积为8 773 410μm2,功耗为724.920 4 mW。在ULTRA60上运行时间为14 h。

In this paper an efficient logic synthesis strategy for very large scale SoC is introduced. The idea is inserting clock gating ceils into the block whose power consumption is large. Furthermore, we use the tool to characterize the constraints of the block not having clock gating cells inserted and then compile the corresponding block with the constraints. Thus the main clock frequency, area and power consumption of our SoC chip are optimized. Furthermore, it is quick to achieve timing closure. We synthesized a SoC chip using our method and got a result better than that of the traditional method. The main frequency of our chip is 200 MHz in the worst case and the area is 8 773 410μm^2. The power consumption is 724. 920 4 mW and the run time on the ULTRA60 is 14 hours.