高吞吐率可变长码解码器的设计与实现

Design and Implementation of High Throughput Variable Length Decoder

可变长码是视频压缩中常用的熵编码方式,因为码字的长度不固定,可变长码的解码器设计往往是整个视频解码器的难点之一.针对视频解码对可变长码解码器解码速率的要求,提出了多路并行解码的方案,排除了长度信息的反馈迟延对解码速率的制约.对解码过程中使用的分组信息表和解码符号表进行了改进,提出伪基础地址查表的方法,使分组信息表相对于同类解码器占用存储资源减小1/3,运算也相应简化.本方案可以在时钟频率为74.25 MHz的FPGA平台工作,可成为高清晰度数字电视解码器的组成部分.

Variable length code is a general lossless entropy coding method, which is widely used in video compress standards. This paper proposed a multi-channel paralleled VLC decoder scheme, which can match the strict requirement of high bit rate video decoding applications. Two tables used in the decoding process were also improved. By using the pseudo base address method, the group information table is reduced to 2/3 in size. This method can get the address with less operation. The simulation results show that this architecture can decode one symbol per system clock at 74.25 MHz clock rate. This design can be used as one important component of HDTV decoder.