期刊文献+

电能质量监测系统中大容量存储设备的研制

Design of Mass Storage Device in Power Quality Meter
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摘要 研制了用于电能质量监测系统中的大容量存储设备,提出了基于USB总线技术和F lash大容量存储技术的硬件系统结构,利用即插即用的USB快速接口传送波形数据,利用NAND F lash对数据进行可靠的保存。结合硬件体系结构和各种功能要求,从固件、设备驱动程序和用户应用程序3方面介绍了系统的软件设计。 The design method of mass storage device in power quality meter was introduced and the system structure based on the technology of USB bus and Flash mass storage was presented, which transfer wave data rapidly by PNP USB interface and save the data credibly by NAND Flash. According to the hardware system and every kind of demand, the design method of software, including the firmware, device driver and user application program, was also presented,
出处 《低压电器》 北大核心 2006年第1期28-31,共4页 Low Voltage Apparatus
基金 国家自然科学基金资助项目(50477026)
关键词 大容量存储 USB技术 闪速存储器 mass storage USB technology flash memory
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参考文献5

  • 1McGranaghan M. Trends in Power Quality Monitoring[J]. IEEE Power Engineering Review, 2001, 21(10) : 3 -9,21.
  • 2Axelson 陈逸译.USB大全[M].北京:中国电力出版社,2003..
  • 3CYPRESS Co. Data Sheet of EZ-USB Rev 1 [Z].2002,10.
  • 4潘立阳,朱钧.Flash存储器技术与发展[J].微电子学,2002,32(1):1-6. 被引量:29
  • 5BakerA LczanoJ.施诺等译.Windows 2000设备驱动程序设计指南[M].北京:机械工业出版社,2001..

二级参考文献19

  • 1[6]Lucero E M, Challa N, Feilds J. A 16k-bit smart 5V-only EEPROM with redundancy [J]. IEEE J Sol Sta Circ,1983;18(10): 539-544.
  • 2[7]Van Houdt J.HIMOS - a high efficiency flash EEPROM cell for embedded memory applications [J]. IEEE Trans Electron Device, 1993;40(12):2255.
  • 3[8]Lenzlinger M, Snow E H. Fowler-Nordheim tunneling in thermally grown SiO2 [J].J Appl Phys,1969; 40: 278.
  • 4[9]Hisamune Y S. A high capacitive coupling ration (HiCR) cell for 3 V only 64 Mbit and future flash memories [A]. IEEE IEDM [C]. 1993.1922.
  • 5[10]Ohnakado T. Novel electron injection method using band-to-band tunneling induced hot electron (BBHE) for flash memory with a p-channel cell [A]. IEDM [C].1995. 279.
  • 6[11]Iwata Y. A high-density NAND EEPROM with block-page programming for microcomputer applications [J]. IEEE J Sol Sta Circ,1990;25(4): 417-424.
  • 7[12]Ajika B. A 5V only 16M bit flash EEPROM cell with a simple stacked gate structure [A]. IEDM [C].1990.115.
  • 8[13]Kobayashi S. Memory array architecture and decoding scheme for 3V-only sector erasable DINOR flash memory [J]. IEEE J Sol Sta Circ, 1994; 29(4): 454-460.
  • 9[14]Kim K S. A novel dual string NOR (DuSNOR) memory cell technology scalable to the 256M bit and 1G bit flash memory [A]. IEDM [C].1995.263.
  • 10[15]Dimaria D J. Trap creation in silicon dioxide produced by hot electrons [J]. J Appl Phys, 1989; 65(6): 2342-2355.

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