摘要
设计并实现了T比特路由器中的转发引擎模块,该模块采用基于子模块处理器的并行转发结构,基于FPGA的并行流水线处理技术,结合分段查表算法,实现了10GPOS接口,IPv4/v6双协议栈的线速转发。试验测试表明该引擎能高效、稳定地达到设计目标,充分满足T比特路由器的整体需求。
The forwarding engine of terabit router is designed and implemented. The module adopts parallel forwarding structure based on sub-module processor and parallel pipelining based on FPGA. The subsection routing lookup algorithms is used.They satisfy IPv6 and IPv4/IPv6 dual-stack core touters' OC- 192 (10Gbps) interfaces' wire-speed forwarding. Analysis and experiment prove that the performance of the forwarding engine can reach the design aim effectively and satisfy the whole demands of terabit router.
出处
《计算机工程》
EI
CAS
CSCD
北大核心
2006年第3期251-253,共3页
Computer Engineering
基金
国家"863"信息技术领域重大专项基金资助项目(2002AA103051
2003AA103510)