扩大ARM SoC的验证覆盖缩短仿真时间

Improving Verification Coverage of ARM SoCs while Reducing Simulation Runtime

验证复杂的SoC设计要耗费极大的成本和时间。本文将介绍一个设计实例,使用作为激励的代码和基于断言的验证,通过该实例来描述使用传统验证技术无法发现的设计错误。

The verification of a complex SoC designs is costly and time consuming. We will describe design errors that were uncovered in an example design by using code as stimulus in conjunction with assertion based verification, design errors that would not have been exposed using traditional verification techniques.