多寄存器组网络处理器上的寄存器分配技术

Register Allocation on Network Processors with Multiple Register Banks

针对传统的图着色寄存器分配算法不能直接处理网络处理器的操作问题,提出了一种多寄存器组网络处理上的寄存器分配技术.在依次分析了一个符号寄存器可能位于哪些寄存器组?如果没有候选组,该如何解决这种冲突?如果有多个候选组,该选用哪个组等问题的基础上,通过将这些方法与图着色寄存器分配算法相融合,在IXP上实现了这种多寄存器组的寄存器分配,提高了它的可编程性.这种方法也可运用到其它具有类似寄存器结构的处理器上.

To meet the requirements of network applications, some network processors, like Intel IXP series, apply an unconventional multiple-register-bank architecture. Register banks are connected by data paths such that data can be moved around in the register banks. Moreover, the source or destination operands of an instruction can reside in one or more register banks. Two sources selection rules further restrict the bank selection of the two source operands of an instruction. Facing these new problems, the classical graph coloring register allocation algorithm cannot be directly applied. A series of algorithms are presented to address the problems by answering the following questions. Which legal candidate register banks can a symbolic register reside in？ If the candidate banks are empty, how to resolve the bank conflicts？ And if there＇re multiple candidate banks, which bank should be selected？ After integrating these algorithms with the graph-coloring register allocation, authors have implemented a multiple-register-bank register allocator on IXP, which improved the programmability of IXP. The algorithms can also be applied to other microprocessors with the similar register architecture.