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A Test Approach for Look-Up Table Based FPGAs 被引量：6

A Test Approach for Look-Up Table Based FPGAs
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摘要 This paper describes a test architecture for minimum number of test configurations in test of FPGA （Field Programmable Gate Array） LUTs （Look Up Tables）. The test architecture includes a TPG （Test Pattern Generator） that is tested while it is generating test data for LEs （Logic Elements） that form the CUT （Circuit Under Test）. This scheme eliminates the need for switching LEs between CUT, TPG and ORA （Output Response Analyzer） and having to perform many more reconfiguratioas of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing. This paper describes a test architecture for minimum number of test configurations in test of FPGA （Field Programmable Gate Array） LUTs （Look Up Tables）. The test architecture includes a TPG （Test Pattern Generator） that is tested while it is generating test data for LEs （Logic Elements） that form the CUT （Circuit Under Test）. This scheme eliminates the need for switching LEs between CUT, TPG and ORA （Output Response Analyzer） and having to perform many more reconfiguratioas of the FPGA. An external ORA locates faults of the FPGA under test. In addition to the LUTs, a scheme is presented for testing other parts of LEs. Compared with other methods, the presented scheme uses the least number of reconfigurations of an FPGA for its LUT testing.
作者 Ehsan Atoofian Zainalabedin Navabi
机构地区 Department of Electrical and Computer Engineering
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 2006年第1期141-146,共6页 计算机科学技术学报（英文版）
关键词 FPGA testing BIST LUT testing memory testing TPG with LE FPGA testing, BIST, LUT testing, memory testing, TPG with LE
分类号 TP20 [自动化与计算机技术—检测技术与自动化装置]
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参考文献12

  • 1Metra C et al. Novel technique for testing FPGA. Design, Automation and Test in Europe, Palais des Congres Paris, France,1998, pp,89-94.
  • 2Alderighi M, Gummati E, Piuri V, Sechi G. A FPGA based implementation of a fault tolerant neural architecture for photon identification. In Proc. the Int. Symp. Field-Programmable Gate Arrays, Monterey, CA, USA, 1997, pp.166-172.
  • 3Renovell M, Figueras Jl Zorian Y. Test of RAM-based FPGA: Methodology and application to the interconnect. In Proc,15th VLSI Test Sy,p., Anaheim, USA, 1997, pp,230-237.
  • 4Stroud C, Wijesuriya S, Hamilton C, Abramovici M. Built-in self-test of FPGA interconnect. In Proc. the IEEE Int. Test Conf., Washington DC, USA, 1998, pp.404-411.
  • 5Sun X, Xu J, Trouborst P. Testing Xilinx XC4000 configurable logic blocks with carry logic modules. In Proc. the IEEE Int. Syrnp, Defect and Fault Tolerance in VLSI Systems, San Francisco, CA, USA, October 2001,pp.221-229.
  • 6Renovell M, Portal J M, Figueras J, Zorian Y. RAM-based FPGAs: A test approach for the configurable logic. In Proc. the Design, Automation and Test in Europe, Palals des Congres Paris, France, 1998, pp,82-88.
  • 7Huang W K, Meyer F J, Park N, Lombardi F. Testing memory modules in SRAM-based configurable FPGAs. In Proc. IEEE International Workshop on Memory Technology, Design and Test, San Jose, CA, USA, August 1997, pp.79-86.
  • 8Renovell M, SRAM-based FPGAs: A structural test approach. IEEE Ⅺ Brazilian Symposium on Integrated Circuit Design, Rio de Janeiro, Brazil, Oct, 1998, pp.67-72.
  • 9Inoue T et al. Universal test complexity of field programmable gate arrays. In Proc. Asian Test Symp., Bangalore, India,1995, pp.259-265.
  • 10Stroud C et al. Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). In Proc. VLSI Test Symp., Princeton, N J, USA, 1996, pp.387-392.

同被引文献25

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Journal of Computer Science & Technology
2006年 第1期

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