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考虑热点及热量分布系统级芯片的测试规划 被引量：1

SoC Test Scheduling with Hot-Spot Avoidance and Even Heat Distribution
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摘要 在SoC的测试规划时,考虑为避免在测试过程中出现热点以及测试过程中使热量均匀分布,基于建立的问题模型得到一系列的并行测试集合,再通过Bin-Packing算法构造测试规划,并进行全局的优化.对ITC’02测试用例的实验结果表明,该方法在牺牲一定的测试时间的情况下,有效地控制了在测试时芯片温度的升高,从而避免出现由热量引起的一系列问题. An approach based on Bin-Packing algorithm and graph theory is proposed to avoid the hotspot and distribute heat evenly on chip surface during test scheduling. First several parallel test set （PTSs） are derived from graph models. Then Bin-Packing algorithm constructs an initial test schedule. A global optimal procedure gets the better test schedule finally. Experiment at results on ITC＇02 benchmark SoCs show that this method can effectively avoid hot-spot and distribute heat evenly at the expense of a little percentage of test time.
作者 陈建 赵长虹 周电 周晓方
机构地区 复旦大学专用集成电路与系统国家重点实验室ICCAD研究室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2006年第1期46-52,共7页 Journal of Computer-Aided Design & Computer Graphics
基金 国家"八六三"高技术研究发展计划(2003AA1Z1120 2004AA1Z1050) 国家自然科学基金(90307017 60176017 90207002) 美国国家科学基金(NSFgrantsCCR-0098275 CCR-0306298)
关键词 系统级芯片 测试规划 热点 测试兼容图 SoC test-schedule hot-spot test compatibility graph
分类号 TN407 [电子电信—微电子学与固体电子学]
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参考文献13

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同被引文献10

  • 1Marinissen E J, Prince B, Keitei Schulz D, et al. Challenges in embedded memory design and test [C]//Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Munich, 2005:722-727
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  • 3Shoukourian S, Vardanian V, Zorian Y. SoC yield optimization via an embedded-memory test and repair infrastructure[J]. IEEE Design & Test of Computers, 2004, 21(3): 200-207
  • 4Hobson R F. A new single-ended SRAM cell with wire assist [J]. IEEE Transactions on Very Large Scale Integration (VLSI)Systems, 2007, 15(2): 17:3-180
  • 5Levacq D, Dessard V, Flandre D. Low leakage SOI CMOS static memory cell with ultra low power diode [J]. IEEE Journal of Solid-State Circuits, 2007, 42(3): 689-702
  • 6WangXP, MehlerJ N, MeyerFJ, et al. Memory yield and complexity of built in self-repair[C]//Proceedings of Reliability and Maintainability Symposium, Alexandria, 2005:238-239
  • 7Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep submicrometer CMOS circuits [J]. Proceedings of the IEEE, 2003, 91(2): 305-306
  • 8Yu Y, Zhao Q, Shao Z B. A low power SRAM/SOI memory cell design [J]. Chinese Journal of Semiconductors, 2006, 27 (2) : 318-322
  • 9Ruan X Y, Katti R S. Data independent pattern run length compression for testing embedded cores in SoCs [J]. IEEE Transactions on Computers, 2007, 56(4): 545-555
  • 10肖继学,陈光,谢永乐.VLSI中加法器的一种高效自测试设计[J].计算机辅助设计与图形学学报,2007,19(11):1465-1470. 被引量：3

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计算机辅助设计与图形学学报
2006年 第1期

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