期刊文献+

一种有效的片上系统测试数据压缩算法 被引量:7

Study of an efficient SOC test vector compression scheme
下载PDF
导出
摘要 测试数据的规模和容量直接影响了片上系统的测试成本,故提出了一种测试数据编码的压缩算法———M in Comp.该方法采用不等间距的编码方式,根据测试数据中游程长度的统计分布情况来调整各组数据的大小,从而提高测试数据的压缩率,降低了测试成本.为了使编码算法对应的解码电路的硬件开销最小化,该算法还引入了前后缀标识位的概念,这样可减小解码电路的规模和复杂度.对ISCAS89benchm ark电路的实验结果表明,采用M in Comp编码方式的压缩效率要比Golomb等编码方法好,而且实现方式简单. Test volume is an important factor affecting the cost of the SOC Testing. In order to reduce the cost of SOC Testing, the paper proposes a method for compression/decompression of test data, that is the Min_Comp. Based on the analysis of the different sizes of the run-length coding, the method determines the grouping of test data and it can improve the compression ratio and reduce the test cost. Furthermore, by introducing the prefix and tail flag, the decoder leads to lower hardware overhead compared with those in the references. Experiments were performed on the ISCAS 89 bechmark circuits, and the results show that the Min_Comp code has a better compression ratio than the Gololnb code. Also, the decompression circuit has a low area overhead and is easy to design.
作者 方建平 郝跃
出处 《西安电子科技大学学报》 EI CAS CSCD 北大核心 2006年第1期1-4,10,共5页 Journal of Xidian University
基金 国家"863"高技术项目支持研究(2003AA1Z1130)
关键词 测试数据压缩 哈夫曼编码 Golomb编码 Min_Comp编码 test vector compression Huffman code Golomb code Min Comp code
  • 相关文献

参考文献1

二级参考文献8

  • 1Paschalis A, Gizopoulos D. An Effective BIST Architecture for Fast Multiplier Cores[A]. Design, Automation and Test in Europe Conference[C]. Munich: IEEE, Inc, 1999. 117-121.
  • 2Nakamura S. Algorithms for Iterative Array Multiplication[J]. IEEE Trans on Computers, 1986, 35(8) : 713-719.
  • 3Wallace C S. A Suggestion for a Fast Multiplier[J]. IEEE Trans on Elecronic Computers, 1964, 13( 1): 14-17.
  • 4Takach A B, Jha N K. Easily Testable Gate Level and DCVS Multipliers[J]. IEEE Trans on Computer-Aided Design, 1991, 10(7):932-942.
  • 5Hong S J. The Design of a Testable Parallel Multiplier[J]. IEEE Trans on Computers, 1990, 39(3) : 411-416.
  • 6Margala M, Chen Xianling. Design Verification and DFT for an Embedded Reconfigurable Low-power Multiplier in System-on-chip Applciations[A]. 14th Annual IEEE International ASIC/SOC Conference[C]. Arlington: IEEE, Inc, 2001. 230-234.
  • 7李兆麟,叶以正,毛志刚.内建自测试中多输入特征寄存器的硬件开销的减少[J].微处理机,2001,22(1):14-18. 被引量:1
  • 8蔡晨曦,王秀坛,彭应宁.基于两维压缩特征字分析的BIST性能分析[J].系统工程与电子技术,2001,23(9):1-4. 被引量:1

共引文献3

同被引文献57

引证文献7

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部