H.264/AVC硬件解码器设计及其验证策略

Design of an H.264/AVC Decoder and Its Verification

提出了一种H.264/AVC硬件解码器的SOC/ASIC设计方案,并在实现电路的基础上,重点分析了基于文中的硬件设计方案的验证策略。该设计方案已经在基于FPGA的验证平台上通过功能原型验证,结果证明,这是一个完全可行的H.264/AVC硬件解码设计方案。

An SOC/ASIC solution is presented for H. 264/AVC decoder. Based on the implemented circuit, the verification strategy for this design scheme is analyzed in particular. A functional verification of the prototype circuit was conducted based on an FPGA platform. It has been demonstrated that this scheme is a practical solution to designing H. 264/AVC decoder.