0.18μm射频SOI LDMOS功率器件的研究

A Study on 0.18 μm RF SOI LDMOS Power Device

在提出0.18μm射频SOI LDMOS功率器件研究方法的基础上,对工艺进行了设计,并制备了栅宽为1 200μm,栅长为0.7μm,漏的注入区与栅的距离为1.5μm的0.18μm射频SOILDMOS功率器件。对器件进行了测试和模拟,在工作频率为3 GHz,直流偏置电压VDS为3 V,VGS为1.5 V,输入功率Pin为5 dBm时,Pout、增益和PAE分别为15 dBm1、0 dB和35%。

A study was made on 0.18 μm RF SOI LDMOS power device, and fabrication technology for the device was designed. An RF SOI LDMOS power device with 1 200 μm / 0.7 μm gate-width/length and a 1.5 μm drain-to-gate distance was fabricated using this technology. Simulation and test show that the device has achieved a 15 dBm Pout, , a 10 dB gain and a 35% PAE for 3 GHz operating frequency, with VDS and VGS biased at 3 V and 1.5 V, respectively.