摘要
运动估计是视频压缩中最重要的环节,文章讨论了运动估计的基本原理并分析了其特点,采用了三步分层搜索算法,设计了一种基于MPEG-2的主档次标准的9PE全并行结构的高速运动估计电路,并通过FPGA验证,系统时钟频率达到35MHz,性能达到了实时编码的要求。
Motion Estimation is the most important step in video compression, this paper analyzes the fundamental theory of motion estimation, uses the 3-step hierachical search block-matching algorithm, a fast motion estimation algorithm for video coding, developed a 9 PEs fully parallel high speed motion estimation circuit which based on the main level standard of MPEG-2. We use Synplify Pro 7.3.1 to synthesis it and target it to ALTERA APEX20KE EP20K150OE, the clock frequency is 35MHz and reaches the demand of real-time decoding.
出处
《微电子学与计算机》
CSCD
北大核心
2006年第2期100-103,共4页
Microelectronics & Computer
