锁相环的VHDL-AMS建模与仿真分析

Modeling and Simulation of PLL Based on VHDL-AMS

介绍具有混合信号系统描述能力的硬件描述语言VHDL-AMS的新特性。通过对锁相环路进行数学分析,建立锁相环的VHDL-AMS模型,并进行仿真分析。从文中可以看出,应用VHDL-AMS,使得锁相环的仿真设计更加简捷有效。

VHDL-AMS is introduced, which is Analog and mixed signal extensions to IEEE standard VHDL. And PLL is implemented based on VHDL-AMS by mathematical formula. Simulation result of PLL is presented. Design of PLL is simplified by VHDL-AMS because of its capacity of modeling analog circuits and mixed signal systems.