高效GOLAY序列相关器的FPGA实现

An Efficient Golay Sequence Correlator and Its FPGA Implementation

介绍了二进制互补GOLAY序列及其FPGA(现场可编程门阵列)实现。首先介绍了GO-LAY序列递归生成方式,由此导出了高效GOLAY序列相关器的滤波器实现结构。高效GOLAY序列相关器算法实现复杂度低,特别适用于高速数据传输的情况。然后介绍了基于FPGA的实现方案,并且进一步提出了改进方案,大大节省了硬件资源。相对于传统的串行或并行相关器,高效GOLAY序列相关器在节约硬件资源和提高工作频率上都有很大的优势。硬件仿真结果表明,该结构能满足高速数据传输的快速计算要求,且硬件资源占用很少。

Binary Golay complementary sequences are introduced and its efficient Golay correlator （EGC）, which has low implementation complexity, is derived, and the FPGA implementation is given. Results show that EGC has advantage over traditional serial or parallel correlator in terms of resources saving and achieving high working frequency.