利用VHDL设计电路的简化问题

Discussed Simplify Problem of Design Circuit with VHDL

利用VHDL设计电路是目前对于较复杂的电路系统进行设计时的最好选择,但设计中如何进行电路的简化直接关系到电路的复杂度及可靠性。本文分析了VHDL设计中容易引起电路复杂化的原因,提出了相应的解决方法。

Make use of VHDL design circuit is a best choice toward complex circuit system design at present. But how simplify circuit directly relation that its complication and reliability in circuit design. This paper analysis to give rise to circuit complication reason in design of VHDL and expound solve method.