一种基于FPGA的顺序迭代FFT设计

A Fully Sequential Iterative FFT Design Performed by FPGA

本文从顺序迭代的角度提出了一种高效的,容易实现的,占用资源少的FFT算法结构,通过合理的设计使得系统占资源少而且高效,同时亦足够简单。本文详细描述了整个设计,在精简程度、完全的流水化、控制结构方式、蝶形运算、时序配合、存储地址生成等方面均有一些特点。

This paper puts forward a new FFT design performed by FPGA. It is based on sequential iterative structure. It is simple, efficient, easy-impletemented and it uses less resources. This paper describes the design fully and clearly. The design has its own cbaracteristics in reduction, pipe-line design, control structure, butterfly unit calculation, sequential timing and address generation.