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深亚微米集成电路静态功耗的优化 被引量：6

Optimization of Standby Power in Deep Sub-micron Integrated Circuits
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摘要 随着工艺的发展,器件阈值电压的降低,导致静态功耗呈指数形式增长。进入深亚微米工艺后,静态功耗开始和动态功耗相抗衡,已成为低功耗设计一个不可忽视的因素。针对近年来提出的各种降低静态功耗的设计方法,本文进行了总结。对源极反偏法、双阈值法、变阈值法、多阈值法的原理和应用进行了分析和说明,并通过对各种方法的优缺点进行比较,旨在为集成电路设计人员提供减小静态功耗方面的设计思路和努力方向。 As technology evolves, the threshold voltage will be reduced accordingly, which results in an exponential increase of standby power. In deep sub-micron technology, the mount of the static power catches up with the dynamic power gradually and the standby power is becoming an important factor in low power design. In recent years, many methods of reducing static power has been presented. These methods will be summarized in this paper. In addition, the principle and application using source biasing, dual Vt partitioning, variable threshold method, multi-threshold method is analyzed and described, advantage and disadvantage in these methods are compared, to provide IC designers a reference in low power design.
作者 石乔林 李天阳 田海燕
机构地区 江苏无锡江南大学信息工程学院 江苏无锡中国电子科技集团
出处 《微计算机信息》 北大核心 2005年第12Z期138-141,共4页 Control & Automation
关键词 静态功耗 亚阈值电流 阈值电压 集成电路 standby power sub-threshold current threshold voltage
分类号 TN47 [电子电信—微电子学与固体电子学]
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参考文献13

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二级参考文献20

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共引文献2

同被引文献33

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引证文献6

二级引证文献1

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2005年 第12Z期

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