基于通用PC架构的高精度网络时延测量方法

A High Precision Approach of Network Delay Measurement Based on General PC

时延是准确测量时延抖动、带宽等网络性能指标的基础．目前的时延测量方法由于存在时钟误差和位置误差因而精度较差．提出一种改进的时延测量方法，以TSC（time stamp counter）寄存器取代系统时钟计时来消除测量的时钟误差，将时间戳记录位置由应用程序转移到网卡驱动来消除位置误差，极大地提高了时延测量精度．实验结果表明，与传统方法相比，不同包长度下，所提出的方法可降低测量误差21％～150％，且测量结果稳定，对系统吞吐量基本无影响．该方法基于通用PC架构，测量成本低，适于普遍采用．

Delay is the foundation for accurately measuring network performance metrics such as delay jitter, bandwidth, etc. While the delay measurement methods currently used have poor p recision, for there exist clock errors and location errors. In this paper, an improved method for delay measurement is proposed. It replaces system clock with TSC （time stamp counter） register as time-stamping to eliminate clock errors, and it removes the time-stamping place from application to network driver to eliminate location errors. The precision has been elevated largely. Experiments show that when comparing with traditional methods under different packet lengths, the improved method can reduce measurement errors 21%～150%, and the measured delays are more stable. Furthermore, it basically has no effect on system throughput. The improved measurement method is based on general PC, so it has lower measurement cost and can be applied widely.