改进的扫描森林测试结构

Improved scan forest architecture

为了降低可测试性设计的面积开销和布线难度,提出了扫描森林结构的重组策略;为了避免故障屏蔽,提出了基于电路结构信息的异或树构造策略。将以上策略应用于ISCA S89和ITC 99基准电路,其中电路s38584的叶结点数由1 318降低到120,被屏蔽故障数由1 376降低到0。实验结果表明:改进的扫描森林测试结构保持了原结构在降低测试时间、测试功耗和测试数据量方面的优势,同时降低了面积开销和布线难度,避免了故障屏蔽。

A scan forest reorganization scheme was developed to reduce design for testability （DFT） area overhead and routing complexities, Aliasing faults were avoided with an exclusive or tree construction scheme based on the circuits＇ structural information. Application of the schemes to ISCAS89 and ITC99 circuits, such as circuit s38584, reduced the number of leaf nodes from 1 318 to 120, with the number of aliasing faults reduced from 1376 to 0. Experiments show that the architecture significantly reduces test application time, test power, and test data volume, with low DFT area overhead, and no aliasing faults.