降低泄漏电流的细粒度休眠晶体管插入法(英文)

Fine-Grain Sleep Transistor Insertion for Leakage Reduction

首先给出一种泄漏电流和延时的简化模型,并且在此基础上提出了一种降低泄漏电流的细粒度休眠晶体管插入法.该方法的核心是利用混合整数线性规划方法同时确定插入细粒度休眠晶体管的位置和尺寸.从实验结果可以发现,由于这种方法更好地利用了电路中的延时余量,所以在电路性能不受影响的情况下可以减小79.75%的泄漏电流;并且在一定范围内放宽电路的延时约束可以更大幅度地降低泄漏电流.与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积.

A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming （MLP） problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.