嵌入式处理器的TLB电路设计

Design of TLB for Embedded Processor

为了提高基于虚拟存储技术的嵌入式处理器的性能,本文提出了一种用于高效加速地址转换的TLB电路结构。该电路采用64-en tries的全关联结构,硬件支持基于段及不同大小页的转换方式。通过VCS和N anosim联合仿真对电路结构和性能进行了验证,仿真结果表明,系统中加入TLB电路以后性能有显著的提高。

In order to improve the performance of the embedded processor based on virtual memory, this paper proposes a viable structure of TLB which used to speed up the transition of addresses. It is fullyassociated with 64 entries, and can support the transition based on section and different page sizes. We use the tool of VCS together with Nanosim to do the simulation. The result by using the TLB shows that the performance of system can be grealty improved.