摘要
介绍了基于CPLD和EDA技术的BIT(机内测试)系统的实现。本系统以CPLD为控制核心,在MAX+PLUSII环境下采用VHDL语言实现了系统接口及测频电路。该系统具有集成度高、灵活性强、易于开发、维护、扩展等特点。
The development of a BIT system based on CPLD and EDA technology is introduced. The CPLD is the control core in this system. With the VHDL language under MAX＋PLUSII environment, the system interface and frequency measurement are realized. As a result, it is easy to update, to maintain and to expand.
出处
《微计算机信息》
北大核心
2006年第03Z期177-178,共2页
Control & Automation
基金
总装备部基金项目。
