基于Verilog　HDL的数字集成电路高层设计环境

High Level Design Environment for Digital Integrated Circuit Based on Verilog HDL

基于ＶｅｒｉｌｏｇＨＤＬ硬件描述语言以及ＶｅｒｉｌｏｇＸＬ模拟器，建立了从行为描述到寄存器传输级设计生成的数字集成电路高层设计环境，重点介绍了功能单元库的建立、目标硬件结构构成、排序与硬件配置．最后给出了一个设计实例．

A high level design environment for digital integrated circuit from behavioral specification to register transfer level is set up, based on Verilog hardware description language and Verilog XL simulator. Establishing functional unit library, structuring initial target architccture,scheduling and allocating are described. Finally, an example is given.