隔N位一抽头的串入并出CCD多抽头延迟线

Series in/Parallel Out CCD Multi-Tapped Delay Line with a Tap Interval of N-Bit

本文将介绍串入并出抽头延迟线的基本原理、器件结构,特别是抽头与非抽头的时钟电极结构。

The principle and device configuration of the series in/parallel out CCD tapped delay line with a tap interval of N-bit are described with the emphasis on the configuretion of tapped and non-tapped clock electrodes.