应用于VLSI的PSSWS-LDD MOSFET优化工艺研究

Study of PSSWS-LDD MOSFET Optimum Process Conditions for VLSI

提出实现VLSI的PSSWS(Poly Silicon Side Wall Spacer)—LDD(Lightly DopedDrain)结构,研究了它的形成工艺,获得多晶侧壁形成的优化工艺条件,制作出亚微米有效沟道长度的LDD NMOSFET。在器件性能研究和计算机模拟的基础上,得到PSSWS—LDDMOSFET的优化工艺实现条件;此条件下实现的有效沟道长为0.8μm的PSSWS—LDDNMOSFET,源漏击穿电压达20V,常规器件的小于16V;衬底电流较常规器件的减小约二个数量级。利用此优化条件,研制出高性能的1μm沟道长度的CMOS CD4007电路,2μm沟道长的21级CMOS环振,LSI CMOS 2.5μm沟道长度的门阵列电路GA 300 5SD。结果表明:PSSWS—LDD MOSFET性能衰退小,速度快,可靠性高,适用于VLSI的制造。

A Poly-Silicon Side Wall Spacer (PSSWS-) LDD structure for VLSI is proposed, the technologyis studied,and the optimized process conditions for vealizing PSSWS-LDD have beenobtained.The PSSWS-LDD NMOSFETs with an effective channel length of 0.8μm have beenfabricated by using the optimized process conditions.The sourcedrain breakdown voltage isabout 20V, and substrate current is about two orders of magnitude less than the conventionalone. Using the optimum process conditions,a CMOS circuit Cd4007 with a channel lengthof 1μm, a 21 stages CMOS oscillator with a channel length of 2μm, and a LSI CMOS gate arraywith a channel length of 2.5μm have also been fabricated with high performance. PSSWSLDDMOSFET is of high-speed, high-stability and is suitable for VLSI.