用FPGA实现虚拟逻辑状态分析仪多种功能

Implementation of varied functions of virtual logic state analyzer by FPGA

文中提出使用FPGA实现虚拟逻辑分析仪的多种功能的方法。采用VerilogHDL硬件描述语言设计功能模块,用EDA工具进行仿真、综合,实现虚拟逻辑状态分析仪的多种触发、存储功能。

A method to implement varied trigger functions of Virtual Logic Analyzer using FPGA is presented. Verilog HDL is used in programming of Function blocks. EDA software is used in synthesizing and simulating. Varied trigger and storage functions of Virtual Logic State Analyzer are implemented.