SDH信号中任意抽取时隙的识别方法及FPGA实现

Method to identify any time slots in SDH signal and achievement on FPGA

提出了一种实时有效的对任意抽取时隙的识别方法,适用于SDH机制光纤网络。同时,还提出了2种在FPGA上的实现方案,对方案二进行了较详细的描述。最后用Altera公司提供的开发软件Quartus5.0下的信号采集工具SignalTap对方案二的实现进行了验证。

This paper advances a method to identify any time slots, which is used for Fiber-eptic Communication based on SDH （Synchronous digital hierarchy）, and puts forward two measures to realize the method on FPGA （Field Programmable Logic Array）, and describe the second measure in detail, in the end, the second measure is proved by using the SignalTap, which is a signal sampling tool in exploiture software Quartus5.0 of Altera Company.