一种500MHz高性能锁相环的设计

Design of a Super Performance 500 MHz Phase-Locked Loop

随着专用集成芯片(ASIC)和系统芯片(SOC)的飞速发展,芯片内部生成可变频率的稳定时钟变得至关重要,设计一个高性能锁相环正是适应了这样的需求。本文在传统锁相环结构的基础上设计了一种高速、低功耗、低噪声的高性能嵌入式混合信号锁相环结构。它可以在片内产生多分组高频稳定时钟信号,从而为先进的专用集成芯片(ASIC)和系统芯片(SOC)的实现提供最基础且最重要的可应用时钟产生电路。模拟结果表明:该锁相环可稳定输出500MHz时钟信号,稳定时间小于700ns,在1.8V电源下的功耗小于18mW,噪声小于180mV。

With the development of the ASIC and SO（2, a stable frequency-variable clock in the chip is becoming critical, for which a high-performance phase-locked loop is intended. Based on the traditional phase-locked loop circuit, a high-performance inbuilt mixed-signal phase-locked loop circuit is designed. It can generate multiple rated clocks and provide a most important applicable clock-generating circuit for the design of the current ASIC and SOC. Simulation results show that the circuit has a higher output frequency of 500 MHz, a smaller settling time of 700 ns, a lower power consumption of 18 mW at 1.8 V. What＇s more, the noise is less than 180 mV.