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TABULAR TECHNIQUES FOR OR-COINCIDENCE LOGIC 被引量:12

TABULAR TECHNIQUES FOR OR-COINCIDENCE LOGIC
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摘要 The map folding method for the conversion between Boolean expression and COC expansions is analyzed. Based on it, the tabular techniques are proposed for the conversion between Boolean expression and COC expansion and for the derivation of GOC expansions with fixed polarities. The Fast Tabular Technique (FTT) for the conversion from the Boolean expression to the GOC expansion with the required polarity is also proposed. The simulative result shows this FTT is faster than others in references because of its inherent parallelism. The map folding method for the conversion between Boolean expression and COC expansions is analyzed. Based on it, the tabular techniques are proposed for the conversion between Boolean expression and COC expansion and for the derivation of GOC expansions with fixed polarities. The Fast Tabular Technique (FTT) for the conversion from the Boolean expression to the GOC expansion with the required polarity is also proposed. The simulative result shows this FTT is faster than others in references because of its inherent parallelism.
出处 《Journal of Electronics(China)》 2006年第2期269-273,共5页 电子科学学刊(英文版)
基金 Supported by the National Natural Science Foundation of China (No.60273093) the Natural Science Foundation of Zheiinag Province (No.Y104135)
关键词 Tabular technique OR-coincidence logic Fixed polarity OR-coincidence expansion 快速列表技术 FTT 一致性 逻辑函数 固定极性 COC扩展
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  • 3Najm Farid N. A survey of power estimation techniques in VLSI circuits [ J ]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994, 2(4): 446-455
  • 4Panda Rajendran, Najm Farid N. Technology decomposition for low-power synthesis [ C] //Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, Santa Clara, California, 1995 : 627-630
  • 5Tan E C, Yang H. Optimization of fixed-polarlty Reed-Muller circuits using dual-polarlty property [J]. Circuits Systems Signal Process, 2000, 19(6): 535-548
  • 6Cheng J, Chen X, Faraj K M. Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion [J]. IEE Proceedings Computers and Digital Techniques, 2003, 150(6): 397-402
  • 7Wang L, Almaini A E A. Optimisation of Reed-Muller PLA implementations [J]. IEE Proceedings Circuits, Devices & Systems, 2002, 149(2):119-128
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  • 9Roy Kaushik, Prasad Sharat C. Low-power CMOS VLSI circuit design [M]. New York: John Wiley & Sons, 2000
  • 10H Rahaman, D K Das, B B Bhattacharya. Testable design of AND-EXOR logic networks with universal test sets [J]. Computers and Electrical Engineering, 2009, 35(5): 644-658.

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