计算密集型体系集成DDR SDRAM控制器设计

Design of the DDR SDRAM Controller Integrated by the Data Intensive Computing Architecture

文章介绍了计算密集型体系解决存储器访问瓶颈的研究趋势。针对计算密集型体系的高数据访存需求,提出并在FPGA上实现了一种集成的DDR SDRAM控制器,其关键部分为固化初始化系列和专有的定制系统总线。仿真结果和分析表明,该控制器解决了计算密集型体系的数据访问瓶颈。

The paper introduces the research trend for the access bottleneck between the data intensive computing architecture and memory. Aiming at the high needs for the data intensive computing architecture＇s access to memory, an integrated DDR SDRAM controller is presented and prototyped in FPGA. The key points for the DDR SDRAM controller are a fixed initiation procedure and its dedicated custom system bus. Simulation results and analysis demonstrate the controller basically conquers the access bottleneck between the data intensive computing architecture and memory.